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Voltage Doubler Circuit

Circuit Diagram Schematic Diagram for a Voltage Doubling Circuit (capacitor values are in microF) This is a circuit that outputs a voltage Vout that is approximately twice the level of the Vcc voltage.     The circuit uses a 555 timer IC configured as an astable multivibrator, i.e., it generates a continuous square wave signal of a set frequency as long as its reset pin (pin 4) is held high.  This means that the 555 output toggles between '1' and '0' continuously at the set frequency.     When the circuit is powered up and the 555 output (pin 3) goes to logic '1' for the very first time, its near-Vcc voltage level causes C3 to charge up through D2 and also reach near-Vcc level. When the output goes to logic '0', C2 charges from Vcc through D1, also to a near-Vcc level.  When the 555 output goes back to logic '1' again, C3 may still have some (if not most) of its charge left, and will allow to charge up to a higher level since it is now effectivel...

Frequency Doubler with 4011

Description This frequency doubler uses one CMOS quad, two input NAND gate package type 4011. The frequency doubler proper consists of an inverter IC1B, two differentiating networks R1/C1, R2/C2 and NAND gate IC1A, IC1C and IC1D function as input and output buffers. In Fig.2 exist the pulses in different points of circuit. Circuit diagrams Source  http://users.otenet.gr/~athsam/frequency_doubler_with_4011.htm